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INTEGRATED CIRCUITS
DATA SHEET
TDA8046 Multi-mode QAM demodulator
Product specification Supersededs data of 1996 Jul 23 File under Integrated Circuits, IC02 1996 Nov 19
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 FEATURES APPLICATION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Functional description of the individual blocks Quadrature demodulator and half Nyquist filter Equalizer Lock detector Carrier recovery Clock recovery AGC Offset control Loop amplifiers Output formatter Boundary scan I2C-bus interface I2C-bus write parameters I2C-bus read parameters LIMITING VALUES THERMAL CHARACTERISTICS DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS LOCK DETECTOR CHARACTERISTICS CARRIER RECOVERY CHARACTERISTICS CLOCK RECOVERY CHARACTERISTICS AGC CHARACTERISTICS INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
TDA8046
1996 Nov 19
2
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
1 FEATURES
TDA8046
* Input format: Straight binary or 2's complement (up to 9 bits, TTL compatible) * Output format: 8-bit wide bus (CMOS compatible) * I2C-bus interface to initialize and monitor the demodulator. When no I2C-bus usage; 64-QAM, 20% roll-off factor in default mode * 5 V peripheral and analog supply voltage * 3.3 V core supply voltage * Boundary scan test. 2 APPLICATION
* Different modulation schemes: 4, 16, 32, 64 and 256-QAM * Digital demodulator and square root raised cosine Nyquist filter with roll-off of 15% or 20% * High performance adaptive equalizer (no training sequence needed) * Digital detectors for generation of required control voltages for carrier recovery, clock recovery and AGC * Digital-to-analog converters and operational amplifiers allowing high flexibility for selection of the (PLL) loop time constants * High maximum symbol rate (rs) of 7 Msymbols/s 3 QUICK REFERENCE DATA SYMBOL VDDD(core) VDDD VDDA IDDD(core) IDDD IDDA rs IL SNRlock PARAMETER core supply voltage digital peripheral supply voltage analog supply voltage core supply current digital peripheral supply current analog supply current symbol rate implementation loss Nyquist roll-off (programmable) signal-to-noise ratio for locking a 64-QAM constellation signal-to-noise ratio for locking a 256-QAM constellation Notes note 2
Demodulation for digital cable TV and cable modem.
CONDITIONS
MIN. 3.00 4.75 4.75
TYP. 3.30 5.00 5.00 100 14 16 - 0.7 15 or 20 - -
MAX. 3.60 5.25 5.25 - - - 7 - - - - V V V
UNIT
VDDD(core) = 3.3 V; note 1 - VDDD = 5 V; note 1 VDDA = 5 V; note 1 - - - - - 21 27
mA mA mA Msym/s dB % dB dB
1. The supply currents are specified for the maximum symbol frequency. 2. The implementation loss (IL) of the demodulator is defined as the distance between the measured and theoretical BER curve as function of signal-to-noise ratio at a BER = 10-6 for a back-to-back measurement at the IF frequency. This performance depends on the chosen loop parameters (see Application notes). 4 ORDERING INFORMATION TYPE NUMBER TDA8046H PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT319-2
1996 Nov 19
3
5
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1996 Nov 19 BLOCK DIAGRAM
TEST1 TEST2 TEST3 TCK TRST TDI TDO TMS VDDD1 to 9 VSSD1 to 12 41 43 48 47 6, 13, 16, 25, 33, 38, 45, 51, 63 7, 12, 14, 17, 24, 26, 31, 34, 46, 50, 61, 64 44 40 39 42 BOUNDARY SCAN TEST
Philips Semiconductors
SDA
36
SCL
35
A0
37
I2C-BUS CONTROL
CLOCK GENERATOR OFFSET CONTROL 20 to 23 27 to 30 32 18 FINE AGC CONTROL
TDA8046
to DACs internal clock for digital processing
CLK
62
Multi-mode QAM demodulator
CLKADC
15
4rs
rs 2rs
DIN0 to DIN8 OFFSET FINE AGC EQUALIZER SQUARE ROOT RAISED COSINE
1 to 5, 8 to 11 DIGITAL PHASE ROTATOR OUTPUT FORMATTER
SQUARE ROOT RAISED COSINE
DO7 to DO0 CLKOUT CLKSDV
INPUT REPRESENTATION
DEMODULATOR
4
CLOCK RECOVERY NCO CONTROL CARRIER RECOVERY Iref1 DAC Vref Vref BIAS GENERATOR Vref Iref2
PRESET
49
CLKT
19
COARSE AGC
DAC
ANALOG SECTION
Iref1 Iref2 Iref3
DAC
Iref3 Vref
53 60 VDDA VSSA VCLKTC VCLKREC 59
54
57
58
52 IBIAS
55
56
MGG198
VAGCTC VAGC
VCARTC VCARREC
Product specification
TDA8046
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
6 PINNING SYMBOL DIN0 DIN1 DIN2 DIN3 DIN4 VDDD1 VSSD1 DIN5 DIN6 DIN7 DIN8 VSSD2 VDDD2 VSSD3 CLKADC VDDD3 VSSD4 CLKSDV CLKT DO7 DO6 DO5 DO4 VSSD5 VDDD4 VSSD6 DO3 DO2 DO1 DO0 VSSD7 CLKOUT VDDD5 VSSD8 SCL SDA A0 VDDD6 TEST3 TEST2 1996 Nov 19 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I I I I supply supply I I I I supply supply supply O supply supply O I O O O O supply supply supply O O O O supply I supply supply I I/O I supply I I digital input bit 0 (LSB) digital input bit 1 digital input bit 2 digital input bit 3 digital input bit 4 digital peripheral supply voltage 1 (+5 V) digital ground 1; for input peripheral and core digital input bit 5 digital input bit 6 digital input bit 7 digital input bit 8 (MSB) digital ground 2; for core and clock buffers DESCRIPTION
TDA8046
digital supply voltage 2; for core and clock buffers (+3.3 V) digital peripheral ground 3 clock output to ADC (4 x rs) digital peripheral supply voltage 3 (+5 V) digital ground 4; for core clock symbol data valid output for test purpose only parallel data output (bit 7) parallel data output (bit 6) parallel data output (bit 5) parallel data output (bit 4) digital peripheral ground 5 digital peripheral supply voltage 4 (+5 V) digital ground 6; for core parallel data output (bit 3) parallel data output (bit 2) parallel data output (bit 1) parallel data output (bit 0) digital peripheral ground 7 output formatter clock output digital peripheral supply voltage 5 (+5 V) digital peripheral ground 8 serial clock input (I2C-bus) serial data input/output (I2C-bus) hardware address input (I2C-bus) digital peripheral supply voltage 6 (+5 V) test input 3 (normally connected to ground) test input 2 (normally connected to ground) 5
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
SYMBOL TEST1 TRST TCK TMS VDDD7 VSSD9 TDO TDI PRESET VSSD10 VDDD8 IBIAS VAGCTC VAGC VCARTC VCARREC VCLKTC VCLKREC VSSA VDDA VSSD11 CLK VDDD9 VSSD12
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
I/O I I I I supply supply O I I supply supply I O O O O O O supply supply supply I supply supply
DESCRIPTION test input 1 input (normally connected to ground) optional asynchronous reset input dedicated test clock input input control signal digital supply voltage 7; for core (+3.3 V) digital ground 9; for core serial test data output serial test data input set device into default mode input digital ground 10; for the digital section of the analog block digital supply voltage 8; for the digital section of the analog block (+5 V) input bias current for DACs inverted operational amplifier input voltage for loop filtering analog output voltage for AGC inverted operational amplifier input voltage for carrier recovery loop filtering analog output voltage for carrier recovery inverted operational amplifier input voltage for clock recovery loop filtering analog output voltage for clock recovery analog ground analog supply voltage (+5 V) digital ground 11; for clock clock input (4 x rs) digital supply voltage 9; for clock digital peripheral ground 12
1996 Nov 19
6
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
56 VCARREC
58 VCLKREC
53 VAGCTC
55 VCARTC
57 VCLKTC
64 VSSD12
61 VSSD11
63 VDDD9
54 VAGC
60 VDDA
59 VSSA
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DIN0 1 DIN1 2 DIN2 3 DIN3 4 DIN4 5 VDDD1 6 VSSD1 7 DIN5 8 DIN6 9 DIN7 10 DIN8 11 VSSD2 12 VDDD2 13 VSSD3 14 CLKADC 15 VDDD3 16 VSSD4 17 CLKSDV 18 CLKT 19 DO7 20 DO6 21 DO5 22 DO4 23 VSSD5 24 VDDD4 25 VSSD6 26 DO3 27 DO2 28 DO1 29 DO0 30 VSSD7 31 CLKOUT 32
52 IBIAS 51 VDDD8 50 VSSD10 49 PRESET 48 TDI 47 TDO 46 VSSD9 45 VDDD7 44 TMS 43 TCK 42 TRST 41 TEST1 40 TEST2 39 TEST3 38 VDDD6 37 A0 36 SDA 35 SCL 34 VSSD8 33 VDDD5
MGG197
62 CLK
TDA8046
Fig.2 Pin configuration.
1996 Nov 19
7
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7 FUNCTIONAL DESCRIPTION
TDA8046
currents which are then integrated by a loop filter. To perform this loop filtering, an operational amplifier is integrated after each DAC. The carrier recovery consists of a two-loop system. The outer loop is shown in Fig.3, and controls both phase and frequency at a low speed. The inner loop controls the carrier phase at a high speed (wide loop bandwidth). The AGC also consists of two loops; the outer loop is the coarse AGC and one inner loop is the fine AGC. The recovered symbols are converted into bits according to a demapping scheme and represented at the output in an 8-bit parallel output format. The QAM demodulator can be initialized and monitored by the I2C-bus interface.
Figure 3 shows the application of the TDA8046 multi-mode QAM demodulator. The frequency of the IF signal (IFQAM) is down converted to a frequency that equals the symbol rate (rs) by a mixer which is driven from a local oscillator with a frequency of fCAR = fIF + rs. After low pass filtering this baseband signal is applied to an external 8 or 9-bit ADC. For 256-QAM, a 9-bit ADC is preferred, for the other modes an 8-bit ADC is sufficient. The multi-mode QAM demodulator has digital detectors for AGC, carrier recovery and clock recovery. The on-chip DACs translate the detector values to analog control
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RF signal
TUNER
SAW
IFQAM fCAR = fIF + rs
8 or 9 bits LPF ADC
fclk
clock recovery carrier recovery AGC TDA8046 DO7 to DO0 CLKOUT CLKSDV
I2C-BUS
MGG167
Fig.3 Application with multi-mode QAM demodulator.
1996 Nov 19
8
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1 Functional description of the individual blocks
TDA8046
The TDA8046 can handle five different digital modulation schemes; 4, 16, 32, 64 and 256-QAM. These schemes are selectable via the I2C-bus interface. 7.1.1 QUADRATURE DEMODULATOR AND HALF NYQUIST
FILTER
The functional block diagram of the multi-mode QAM demodulator is illustrated in Fig.1. This section describes the individual blocks in the demodulator. After adaptation for the used input format (2's complement or binary), the input signal is demodulated in the I and Q baseband signals which are applied to the inputs of the half-Nyquist filter (equals square root raised cosine). To avoid overloading of the ADC, an AGC detector is placed after the adaptation for the input format. The control value for the clock recovery is generated after half Nyquist filtering. The echoes created in the cable network are reduced significantly in the equalizer. The equalizer produces a `clean' constellation diagram from which the information for the carrier recovery is derived. This constellation is also applied to the output formatter which demaps the transmitted symbols in corresponding bits. The carrier recovery and lock detection functions are based on the equalizer output. The output of the equalizer is applied to an output formatter, which translates the symbol bits to a FEC input format. The digital outputs of the clock recovery, AGC, and carrier recovery section are converted into currents which are integrated by the loop filters. To make these loop filters active, operational amplifiers are integrated on the chip.
Quadrature demodulation is accomplished after selection of the appropriate input format via the I2C-bus. The in-phase and quadrature components are both applied to a half Nyquist filter. In default mode, this filter gives a 20% roll-off half Nyquist shaping. The basic schematic of the quadrature demodulator followed by the half Nyquist filter is shown in Fig.4. The signs of the multiplication factors in the Q-branch can be inverted (I2C-bus bit INVD). When using an 8-bit ADC the LSB of the 9-bit input word should be connected to the positive supply (VDDD). This ensures a symmetrical 2's complement representation which can be multiplied by -1 in a correct (2's complement) way. The overall transfer function of the square root raised cosine filters is shown in Figs 5 and 6. For characteristics see Chapter 10.
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I2C-BUS
9 DIN8 9 to DIN0 BINARY OR TWO's COMPLEMENT +1, 0, -1, 0 0, -1, 0, +1 9 Q I2C-BUS I2C-BUS I
HALF NYQUIST FILTER
HALF NYQUIST FILTER
I2C-BUS
MGG168
Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
5 0
MBG987
-5 relative gain (dB) -15
-25
-35
-45
-55 0 0.25 0.5 0.75 1 1.25 1.5 1.75 relative frequency 2
(
f rs
)
Fig.5 Half Nyquist receiver filter transfer function (20% roll-off).
MGG169
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0 relative gain (dB) -10
-20
-30
-40
-50 0 0.25 0.5 0.75 1 1.25 1.5 1.75 relative frequency 2
(
f rs
)
Fig.6 Half Nyquist receiver filter transfer function (15% roll-off).
1996 Nov 19
10
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.2 EQUALIZER
TDA8046
The equalizer has been proven to work correctly under bad channel conditions as indicated in Table 1. It is guaranteed that all loops (including equalizer) converge at a SNR of 21 dB for a 64-QAM modulation format and 27 dB for a 256-QAM modulation format. Table 1
3
This function is realized with a T spaced 12 or 14 taps (selected via the I2C-bus) adaptive filter with a feedback part. The equaliser is based on a Decision Feedback Equalizer (DFE) structure with Least Mean Square (LMS) coefficient updating algorithm. No training sequence is required. The block schematic of the total equalizer is shown in Fig.8. The main tap of the equalizer is adjustable for fine AGC function (6 dB AGC range). The settings of the equalizer taps can be read via the I2C-bus. If the equalizer diverges, an alarm bit is set (I2C-bus bit ALEQ) and an automatic reset of the taps can be performed (I2C-bus bit EAR). To improve acquisition time, the convergence steps of the FFE/DFE parts of the equalizer are programmable via the I2C-bus. When the system locks, the steps are automatically modified for optimum performances. Besides reading the equalizer tap values, the main tap of the equalizer can also be programmed. After setting the main tap, the other coefficients can be set to zero. The equalizer settings can also be frozen via the I2C-bus.
Channel echo profile AMPLITUDE 0.08 0.20 0.05 0.10 0.03 PHASE 130 60 310 200 200
DELAY
8 x Tsym 1 x T 18 sym
2 x Tsym 458 x Tsym 678 x Tsym
Figure 7 represents the QAM spectrum seen by the equalizer. It corresponds (in the frequency domain) to the multiplication of a full nyquist spectrum by the impulse response of the channel specified in Table 1.
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1
MGD636
relative gain (dB) -1
-3
-5
-7
-9
-11 -0.5
-0.375
-0.25
-0.125
0
0.125
0.25
0.375 relative frequency
0.5
(
f rs
)
Fig.7 QAM spectrum with echo profile as seen by the equalizer.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
input
FEED FORWARD EQUALIZER TAPS CALCULATION
DECISION FEEDBACK EQUALIZER TAPS CALCULATION
decision
-
+
MGG170
output
Fig.8 DFE equalizer structure.
7.1.3
LOCK DETECTOR
The lock detector indicates whether all algorithms in the demodulator are converged or not. For a symbol error rate (at the input of the demodulator) smaller than 2 x 10-2, the detector will give the indication `LOCK' (I2C-bus bit LK = 1). For larger symbol error rates, the detector will generate the `UNLOCK' signal (I2C-bus bit LK = 0). It should ne noted that this `UNLOCK' signal is generated before any other part of the demodulator loses lock. The lock detector is part of the carrier recovery loop, see Fig.9. The Lock Detector Threshold (LDT) can be changed with the help of the I2C-bus. The estimation algorithm used in the lock detector also provides information about the SER ratio which can be read out via the I2C-bus interface. For characteristics see Chapter 11. 7.1.4 CARRIER RECOVERY
1. The outer loop; this loop controls the phase and frequency of the incoming QAM signal at the IF frequency in such a way that the constellation is optimally positioned for detection. 2. The inner loop; the bandwidth of this loop can be large and can therefore reduce the influence of large bandwidth phase noise. A fully digital carrier recovery function is also possible and can be selected via the I2C-bus. Should this configuration be used, then the external components of the loop filter will not have to be implemented. Four different maximum DAC output currents can be selected via the I2C-bus. The output currents of the DAC are defined in such a way that a VCO with a behaviour as shown in Fig.9 can be connected directly to the output of the integrated operational amplifier. Should the VCO slope be negative then the sign of the current can be inverted by the I2C-bus. Figure 10 defines the DAC output currents. For characteristics see Chapter 12.
The carrier recovery detector consists of a Phase-Frequency Detector (PFD) and Phase Detector (PD). Depending on the mode of operation, the carrier recovery is switched either between the phase frequency (no lock) or the phase detector (lock). The carrier recovery consists of the following two loops:
1996 Nov 19
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
VCO external
0 IFQAM ICAR Vref LPF I2C-BUS LOCK rs Iref1 lock I2C-BUS I2C-BUS DAC
ADC
DEMODULATION AND FILTERING
EQUALIZER
PHASE FREQUENCY DETECTOR PHASE DETECTOR
DIGITAL INNER LOOP I2C-BUS lock I2C-BUS
MGG171
Fig.9 Schematic diagram of the carrier recovery.
1996 Nov 19
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
DAC output current ICAR CARI = 1
1/ I 2 CAR
fVCO
CARI = 0
digital input
VCARREC
MGG180
-1/2 ICAR
-ICAR
Ipos = positive output current. Ineg = negative output current. ( I pos - I neg ) I O = -----------------------------2 ( I pos + I neg ) I O = -------------------------------- x 100 ( I pos - I neg )
Fig.10 Definition of the DAC currents and the expected frequency behaviour of the VCO.
1996 Nov 19
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.5 CLOCK RECOVERY
TDA8046
The clock generator generates the required internal clocks from the VCXO clock signal at 4 x rs. The input stage amplifier of this generator enables the designer to supply a low amplitude oscillator signal to the TDA8046. The DAC output current range (ICLK) can be varied via the I2C-bus. The sign of the output current can also be inverted to adjust for the correct sign of the VCXO slope. For characteristics see Chapter 13.
The clock recovery function uses the unequalized I and Q signals, i.e. the half Nyquist filter outputs (see Fig.4). The clock recovery section generates a control value each symbol period. As this algorithm is based on the energy maximization, both main and mid symbols are required at the input. Consequently, the input data rate is twice the symbol rate. The schematic diagram of this detector is illustrated in Fig.11.
handbook, full pagewidth
external
I CLOCK RECOVERY DETECTOR Q
DAC ICLK rs Iref3 Vref
to VCXO
4rs 2rs rs 2 4
from VCXO
MGG172
Fig.11 Schematic diagram of the clock recovery.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
DAC output current ICLK
fVCXO
CLKI = 1
1/ I 2 CLK
CLKI = 0
digital input
VCLKREC
MGG181
-1/2 ICLK
-ICLK
Ipos = positive output current; ICLK. Ineg = negative output current; -ICLK. ( I pos - I neg ) I oCLK = -----------------------------2 ( I pos + I neg ) I oCLK = -------------------------------- x 100 ( I pos - I neg )
Fig.12 The definition of the DAC currents and the expected frequency behaviour of the VCXO for clock recovery.
1996 Nov 19
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.6 AGC
TDA8046
The I2C-bus data on address 08 is a factor 16 smaller than the used AGC threshold ATH. The DAC output current range can be varied via the I2C-bus interface (bits AGCA and AGCB) and the sign of the current can be inverted (bit AGCI). The definition of the DAC currents and the expected frequency behaviour of the AGC is illustrated in Fig.14. For characteristics see Chapter 14.
The AGC estimates the mean power based on the digital input signal and relates this to a peak value for a given constellation. To avoid overloading of the ADC, this estimation of the peak signals is used to control the AGC loop. The implemented AGC covers a range of 20 dB in gain variance. A schematic diagram of the AGC is illustrated in Fig.13. If the SAW filter does not have sufficient adjacent channel attenuation, the AGC threshold can be varied to avoid clipping of the ADC. To do this, the threshold is made programmable via the I2C-bus (byte ATH). Table 2 shows that for each mode, a new ATH value (on address 08) must be set with the help of the I2C-bus. Table 2 AGC threshold values MODE 256, 64, 16 and 4-QAM 32-QAM
ATH (AGC THRESHOLD) 2040 1442
I2C-BUS DATA FOR ADDRESS 08 7F 5A
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external
DIN8 to DIN0
AGC DETECTOR
DAC IAGC
to AGC amplifier Vref ADC
I2C-BUS I2C-BUS IBIAS
rs Iref2
BIAS GENERATOR
Iref2 I2C-BUS
MGG173
Fig.13 AGC schematic diagram.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
DAC output current IAGC AGCI = 1
1/ I 14 AGC
gain
AGCI = 0
digital input
VAGC
MGG182
-1/14 IACG
-IAGC
Ipos = positive output current; ICLK. Ineg = negative output current; -ICLK. ( I pos - I neg ) I oAGC = -----------------------------2 ( I pos + I neg ) I oAGC = -------------------------------- x 100 ( I pos - I neg )
Fig.14 Definition of the DAC currents and the expected frequency behaviour of the AGC.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.7 OFFSET CONTROL 7.1.9 OUTPUT FORMATTER
TDA8046
To compensate offsets in the I and Q branch, due to spurious signals at the symbol frequency at the ADC input, an offset compensation loop is included. This loop forces the constellation to be symmetrically distributed over its four quadrants. This function can be switched off by I2C-bus bit OFFS. 7.1.8 LOOP AMPLIFIERS
The output formatter transforms the detected symbols into bits in accordance with the selected mapping. The TDA8046 has four possible mapping formats which can be selected via the I2C-bus interface. The demapping procedure and the corresponding bits are defined in Fig.16. After demapping the bits are allocated to the output. This output allocation corresponds to one of the selected demapping schemes. By using the I2C-bus, it is possible to obtain the following output formats: * 8 bits parallel * semi-serial * I and Q 8 bits multiplexed. The implemented demapping formats and output bit allocation are illustrated in Figs 17 to 30. 7.1.10 BOUNDARY SCAN
Analog switches are integrated to discharge the loop filter capacitors or for test purposes on application boards (a reference voltage equal to the half of the positive supply voltage VDDA is available at the output of the amplifier when the switches are closed). The I2C-bus bit ANAS controls the three switches simultaneously. A schematic diagram of the loop amplifier and analog switch is illustrated in Fig.15. For characteristics see Chapter 15.
handbook, halfpage
external
The TDA8046H offers the possibility of boundary scan test. The IEEE Standard Test Access Port and Boundary Scan Architecture allows board manufacturers to test board interconnections by using the boundary scan functions. Complete information on boundary scan test is available in "Application note AN96048".
I2C-BUS
DAC
Vref
MGG174
Fig.15 Loop amplifier and analog switch.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
DO7 to DO0 I Q 8 8 DEMAPPING SCHEMES 1 to 4 PARALLEL AND SEMI-SERIAL CLKSCV DO1 to DO0 CLKSCV CLKOUT
MUX I2C-BUS
MGG175
DO7 to DO0 CLKSCV CLKOUT
Fig.16 Schematic diagram of the output formatter.
7.1.10.1
Demapping scheme 1; differential decoding
handbook, full pagewidth
Q
000100 000101 000111 000110 000010 000011 000001 000000 001100 001101 001111 001110 001010 001011 001001 001000 011100 011101 011111 011110 011010 011011 011001 011000
A quadrant 010100 010101 010111 010110 010010 010011 010001 010000 110100 110101 110111 110110 110010 110011 110001 110000
b5 b4 b3 b2 b1 b0 111100 111101 111111 111110 111010 111011 111001 111000 101100 101101 101111 101110 101010 101011 101001 101000 100100 100101 100111 100110 100010 100011 100001 100000
MGG193
I
Bit allocation for 256-QAM: b5, b4, b3, b2, b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Fig.17 Demapping scheme 1; bit allocation: 256-QAM.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
B quadrant 1010 1110 0110 0010 1011 1111 0111 0011 1001 1101 0101 0001 1000 1100 0100 0000
Q
0010 0011 0001 0000
A quadrant 0110 0111 0101 0100 1110 1111 1101 1100
b5 b4 b3 b2 1010 1011 1001 1000
I
1000 1001 1011 1010 1100 1101 1111 1110 0100 0101 0111 0110 0000 0001 0011 0010 0000 0100 1100 1000 0001 0101 1101 1001 0011 0111 1111 1011 0010 0110 1110 1010
C quadrant
D quadrant
MGG183
Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Bit allocation for 64-QAM: b5, b4, b3 and b2; b0 = b1 = 0; b7 and b6 differentially decoded (see Table 3).
Fig.18 Demapping scheme 1; bit allocation: 4-QAM and 64-QAM.
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B quadrant 11 01 10 00
Q
A quadrant 01 00 11 10
b5 b4
I
10 11 00 01 00 10 01 11
C quadrant
D quadrant
MGG184
Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Bit allocation for 32-QAM: not implemented.
Fig.19 Demapping scheme 1; bit allocation: 16-QAM and 32-QAM.
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Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.10.2 Demapping scheme 2; direct translation
TDA8046
handbook, full pagewidth
Q
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110
b7 b6 b5 b4 1111
1111 1110 1101 1100 1011 1010 1001 1000
b3 b2 b1 b0
I
0111 0110 0101 0100 0011 0010 0001 0000
MGG195
Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0.
Fig.20 Demapping scheme 2; bit allocation: 256-QAM.
1996 Nov 19
22
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
Q
000 001 010 011 100 101 110
b7 b6 b5 b3 b2 b1 111 110 101 100
111
I
011 010 001 000
MGG185
Bit allocation for 64-QAM: b7, b6, b5, b3, b2, b1; b4 = b0 = 0. Bit allocation for 32-QAM: not implemented.
Fig.21 Demapping scheme 2; bit allocation: 64-QAM and 32-QAM.
handbook, full pagewidth
b7 b6
Q Q
0 1 1 10 b7 b3 00 01 10 11 11 b3 b2
I
0 01 00
I
MGG186
a. Bit allocation for 4-QAM: b7 and b3; b6 = b5 = b4 = b2 = b1 = b0 = 0.
b. Bit allocation for 16-QAM: b7, b6, b3 and b2; b5 = b4 = b1 = b0 = 0.
Fig.22 Demapping scheme 2; bit allocation: 4-QAM and 16-QAM.
1996 Nov 19
23
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.10.3 Demapping scheme 3; differential decoding: Draft prETS 429: 1994
TDA8046
handbook, full pagewidth
Q
100000 100010 101010 101000 001000 001010 000010 000000 100001 100011 101011 101001 001001 001011 000011 000001 100101 100111 101111 101101 001101 001111 000111 000101
A quadrant 100100 100110 101110 101100 001100 001110 000110 000100 110100 110110 111110 111100 011100 011110 010110 010100
b5 b4 b3 b2 b1 b0 110101 110111 111111 111101 011101 011111 010111 010101 110001 110011 111011 111001 011001 011011 010011 010001 110000 110010 111010 111000 011000 011010 010010 010000
MGG194
I
Bit allocation for 256-QAM: b5, b4, b3, b2, b1, b0; b7 and b6 differentially decoded (see Table 3).
Fig.23 Demapping scheme 3; bit allocation: 256-QAM.
1996 Nov 19
24
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
B quadrant 1100 1101 1001 1000 1110 1111 1011 1010 0110 0111 0011 0010 0100 0101 0001 0000
Q
1000 1010 0010 0000
A quadrant 1001 1011 0011 0001 1101 1111 0111 0101
b5 b4 b3 b2 1100 1110 0110 0100
I
0100 0110 1110 1100 0101 0111 1111 1101 0001 0011 1011 1001 0000 0010 1010 1000 0000 0001 0101 0100 0010 0011 0111 0110 1010 1011 1111 1110 1000 1001 1101 1100
C quadrant
D quadrant
MGG187
Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Bit allocation for 64-QAM: b5, b4, b3 and b2; b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Fig.24 Demapping scheme 3; bit allocation: 4-QAM and 64-QAM.
handbook, full pagewidth
B quadrant 11 10 01 00
Q
A quadrant 10 00 11 01
b5 b4
I
01 11 00 10 00 01 10 11
C quadrant
D quadrant
MGG188
Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Fig.25 Demapping scheme 3; bit allocation: 16-QAM.
1996 Nov 19
25
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
B quadrant 111 010 110 101 100 011 001 000
Q
110 100 000
A quadrant 010 101 001 b5 b4 b3 111 011
I
011 111 001 101 010 C quadrant 000 100 110 000 001 011 100 101 111 D quadrant
MGG189
110 010
Bit allocation for 32-QAM: b5, b4 and b3; b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Fig.26 Demapping scheme 3; bit allocation: 32-QAM.
7.1.10.4
Demapping scheme 4; direct translation: HP8782B/K03
handbook, full pagewidth
Q
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
b3 b2 b1 b0 0000
0000 0001 0010 0011 0100 0101 0110 0111
b4 b5 b6 b7
I
1000 1001 1010 1011 1100 1101 1110 1111
MGG196
Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0.
Fig.27 Demapping scheme 4; bit allocation: 256-QAM.
1996 Nov 19
26
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
Q
111 110 101 100 011 010 001 000
b2 b3 b4 b5 b6 b7
000 001 010 011
I
100 101 110 111
MGG190
Bit allocation for 64-QAM: b7, b6, b5, b4, b3 and b2; b1 = b0 = 0.
Fig.28 Demapping scheme 4; bit allocation: 64-QAM.
handbook, full pagewidth
B quadrant
Q
A quadrant b7 b6 b5 b4 b3
01111 01011 00010 00110
01110 01101 01001 00100 00101 00111 01010 01100 01000 00000 00001 00011
I
11011 11001 11000 10000 10100 10010 11111 11101 11100 10001 10101 10110 11110 11010 10011 10111
C quadrant
D quadrant
MGG191
Bit allocation for 32-QAM: b7, b6, b5, b4 and b3; b2 = b1 = b0 = 0.
Fig.29 Demapping scheme 4; bit allocation: 32-QAM.
1996 Nov 19
27
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
Q Q
1 0 0 b6 b7 11 10 01 00
b4 b5 b6 b7
00 01
I
1 10 11
I
MGG192
a. Bit allocation for 4-QAM: b7 and b6; b5 = b4 = b3 = b2 = b1 = b0 = 0.
b. Bit allocation for 16-QAM: b7, b6, b5 and b4; b3 = b2 = b1 = b0 = 0.
Fig.30 Demapping scheme 4; bit allocation: 4-QAM and 16-QAM.
Table 3
Definition of two MSB's in modulation schemes 1 and 3 QUADRANT OF PREVIOUSLY RECEIVED SYMBOL A B C D A B C D A B C D A B C D PHASE CHANGE (DEGREES) 0 270 180 90 90 0 270 180 180 90 0 270 270 180 90 0 CURRENT OUTPUT BITS SCHEME 1 b7 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 b6 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 SCHEME 3 b7 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 b6 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0
QUADRANT OF CURRENTLY RECEIVED SYMBOL A A A A B B B B C C C C D D D D
Tables 4 and 5 give the output format of the data for semi-serial mode operations. 1996 Nov 19 28
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
Table 4 SLOT DO1 0 1 2 3 4 5 6 7 Note 1. The semi-serial format is only valid for demapping schemes 1, 3 and 4. Table 5 Semi-serial format 16-QAM and 4-QAM; see note 1 16-QAM SLOT DO1 0 1 2 3 4 5 6 7 Note 1. The semi-serial format is only valid for demapping schemes 1, 3 and 4. Sn-1(3) Sn-1(1) X X Sn(3) Sn(1) X X DO0 Sn-1(2) Sn-1(0) X X Sn(2) Sn(0) X X CLKSDV 1 1 0 0 1 1 0 0 DO1 Sn-1(1) X X X Sn(1) X X X DO0 Sn-1(0) X X X Sn(0) X X X 4-QAM Sn-1(7) Sn-1(5) Sn-1(3) Sn-1(1) Sn(7) Sn(5) Sn(3) Sn(1) DO0 Sn-1(6) Sn-1(4) Sn-1(2) Sn-1(0) Sn(6) Sn(4) Sn(2) Sn(0) CLKSDV 1 1 1 1 1 1 1 1 DO1 Sn-1(5) Sn-1(3) Sn-1(1) X Sn(5) Sn(3) Sn(1) X DO0 Sn-1(4) Sn-1(2) Sn-1(0) X Sn(4) Sn(2) Sn(0) X CLKSDV 1 1 1 0 1 1 1 0 DO1 Sn-1(4) Sn-1(2) X X Sn-1(0) Sn(3) Sn(1) X DO0 Semi-serial format 256, 64 and 32-QAM; see note 1 256-QAM 64-QAM
TDA8046
32-QAM CLKSDV 1 1 0 0 1 1 1 0
Sn-1(3) Sn-1(1) X X Sn(4) Sn(2) Sn(0) X
CLKSDV 1 0 0 0 1 0 0 0
1996 Nov 19
29
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.11 I2C-BUS INTERFACE
TDA8046
The TDA8046 is controlled by an I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for selecting READ or WRITE mode. It should be noted that the TDA8046 starts up in accordance with to the settings defined in Tables 7, 8 and 9. Table 6 A6 0 Table 7 Slave address A5 0 WRITE (R/W = 0) ADD 00 01 02 03 04 05 06 07 08 09 0A 0B D7 AGCI INP ANAS - DCA7 FSOL LDT7 - ATH7 - FFEI07 - D6 CLKI RLF OFFS - DCA6 - LDT6 - ATH6 - FFEI06 FSTP2 D5 CARI OUTB AGCB - DCA5 - LDT5 - ATH5 EAR FFEI05 FSTP1 D4 OUTE OUTA AGCA - DCA4 - LDT4 - ATH4 FFEL FFEI04 FSTP0 D3 DEM INVD CLKB OUTF DCA3 - LDT3 - ATH3 EDFE FFEI03 - D2 NYQ CONC CLKA TSEL2 DCA2 DCB2 LDT2 - ATH2 EFFE FFEI02 DSTP2 D1 DPHR CONB CARB TSEL1 DCA1 DCB1 LDT1 WS1 ATH1 EFC FFEI01 DSTP1 D0 RST CONA CARA TSEL0 DCA0 DCB0 LDT0 WS0 ATH0 PRESET FFEI00 DSTP0 A4 0 A3 1 A2 1 A1 1 A0 A0 R/W X
FUNCTION DAC current inversion/general Demodulator DAC/OFFS/switch Digital test/output formatter Digital loop filter B.W. Digital loop filter B.W. Lock detector threshold Lock detector window size AGC detector threshold Equalizer mode Equalizer tap FFEI Equalizer steps
1996 Nov 19
30
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
Table 8 Default settings after reset ADD 00 01 02 03 04 05 06 07 08 09 0A 0B D7 0 1 0 - 0 1 0 - 0 - 0 - D6 1 1 1 - 1 - 0 - 1 - 1 0 D5 0 0 0 - 0 - 0 - 1 0 0 0 D4 1 0 1 - 0 - 1 - 1 1 0 0 D3 1 0 0 0 0 - 1 - 1 0 0 - D2 1 0 1 0 0 1 0 - 1 0 0 0
TDA8046
FUNCTION DAC current inversion/ general Demodulator DAC/OFFS/switch Digital test/output formatter Digital loop filter B.W. Digital loop filter B.W. Lock detector threshold Lock detector window size AGC detector threshold Equalizer mode Equalizer tap FFEI Equalizer steps Table 9 READ (R/W = 1)
D1 0 1 0 0 0 0 0 0 1 0 0 0
D0 0 1 1 0 0 0 0 0 1 0 0 0
FUNCTION VCARREC (4 bits) VCLKREC (4 bits) VAGC (4 bits) Alarm equalizer/ lock detector SER estimation FFEI3 .... FFEI0 DFEI1 .... DFEI7 DFEI8 FFEQ3 .... FFEQ0 DFEQ1 .... DFEQ8 FFEI5 FFEQ5 1996 Nov 19
ADD 00 01 02 03 04 05 ... 08 09 ... 0F 10 11 ... 14 15 ... 1C 1D 1E
D7 - - - - LE7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7
D6 - - - - LE6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6
D5 - - - - LE5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 31
D4 - - - ALEQ LE4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4
D3 CR03 CL03 AG03 - LE3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3
D2 CR02 CL02 AG02 - LE2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2
D1 CR01 CL01 AG01 - LE1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1
D0 CR00 CL00 AG00 LK LE0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
FUNCTION FFEI4 FFEQ4 IF_frequency_shift IF_frequency_shift 7.1.12
ADD 1F 20 21 22
D7 b7 b7 FS7 -
D6 b6 b6 FS6 -
D5 b5 b5 FS5 -
D4 b4 b4 FS4 -
D3 b3 b3 FS3 FS11
D2 b2 b2 FS2 FS10
D1 b1 b1 FS1 FS9
D0 b0 b0 FS0 FS8
I2C-BUS WRITE PARAMETERS
Table 10 I2C-bus write parameters; 1-bit values PARAMETER Input format Inversion demodulator Demodulator Half Nyquist filter Roll-off factor Digital phase rotator General reset Offset Outer loop activation (carrier recovery) Analog switches 1st and 2nd-order loop (inner loop) DAC current inversion INP INVD DEM NYQ RLF DPHR RST OFFS OUTE ANAS FSOL CARI CLKI AGCI BIT VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2's complement straight binary Q-branch = 0 - 1, 0, +1 Q-branch = 0 + 1, 0, -1 by-pass mode normal mode filter in by-pass mode half Nyquist filter on 15% roll-off 20% roll-off off: pass through mode on normal operation reset (with automatic return to normal operation) off on outer loop inactive outer loop active open closed 1st-order loop 2nd-order loop no inversion inversion no inversion inversion no inversion inversion DESCRIPTION
1996 Nov 19
32
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
PARAMETER Equalizer PRESET EDFE EFFE
BIT
VALUE 0 1 0 1 0 1 0 1 0 1 0 1 normal operation
DESCRIPTION coefficient to zero (main tap to 1) normal operation freeze coefficients of DFE part normal operation freeze coefficients of FFE part normal operation freeze centre tap, no fine AGC automatic reset switched OFF automatic reset switched ON 5 taps in FFE part 3 taps in FFE part
EFC [fine AGC (equalizer freeze centre tap)] EAR FFEL
Table 11 I2C write parameters; 2-bit values PARAMETER Window size (lock detector) WS1 0 0 1 1 Output format OUTB 0 0 1 1 DAC carrier recovery (maximum current) CARB 0 0 1 1 DAC clock recovery (maximum current) CLKB 0 0 1 1 DAC AGC (maximum current) AGCB 0 0 1 1 1996 Nov 19 BITS WS0 0 1 0 1 OUTA 0 1 0 1 CARA 0 1 0 1 CLKA 0 1 0 1 AGCA 0 1 0 1 33 50 A 100 A 150 A 200 A 50 A 100 A 150 A 200 A 50 A 100 A 150 A 200 A scheme 1 scheme 2 scheme 3 scheme 4 256 symbols 512 symbols 1024 symbols 2048 symbols DESCRIPTION
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
Table 12 I2C-bus write parameters; 3-bit values BITS PARAMETER CONC Constellation 0 0 0 0 1 CONB 0 0 1 1 0 CONA 0 1 0 1 0 4-QAM 16-QAM 32-QAM 64-QAM 256-QAM DESCRIPTION
TDA8046
Table 13 Convergence step for the equalizer (DFE and FFE parts) DSTP2 FSTP2 0 0 0 0 1 1 1 1 DSTP1 FSTP1 0 0 1 1 0 0 1 1 DSTP0 FSTP0 0 1 0 1 0 1 0 1 CONVERGENCE STEP (LOCK = 0) 2-13 2-13 2-13 2-12 2-12 2-12 2-12 2-11 CONVERGENCE STEP (LOCK = 1) 2-15 2-14 2-13 2-15 2-14 2-13 2-12 2-15
Table 14 I2C-bus write parameters; 4-bit values BITS PARAMETER OUTF Output format 0 0 1 Special test modes 0 0 0 0 TSEL2 0 1 x x x 0 1 TSEL1 0 1 x 0 1 1 1 TSEL0 0 1 x 1 0 1 1 8 bits in parallel I/Q 8 bits multiplexed (equalizer output) semi-serial DO7 to DO4 = carrier recovery DAC input; DO3 to DO0 = AGC DAC input DO7 to DO6 = fine AGC; DO5 to DO0 = clock recovery DAC input DO7 to DO0 = I and Q equal input (I/Q 8 bits multiplexed format) DO7 to DO0 = I and Q equal output (I/Q 8 bits multiplexed format) DESCRIPTION
1996 Nov 19
34
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
7.1.13 I2C-BUS READ PARAMETERS
TDA8046
Table 15 I2C-bus read parameter; 1-bit values PARAMETER Lock detect Alarm equalizer BIT LK ALEQ VALUE 0 1 0 1 no lock lock normal operation (alarm off) divergence detected (alarm on) DESCRIPTION
Table 16 I2C-bus read parameter; ADC carrier recovery; 4-bit value PARAMETER ADC carrier recovery CR03 b3 b2 BITS CR02 CR01 b1 CR00 b0 carrier recovery: VCARREC = 0.25 + 116VDDD (8b3 + 4b2 + 2b1 + b0) V DESCRIPTION
Table 17 I2C-bus read parameter; ADC clock recovery; 4-bit value PARAMETER ADC clock recovery CL03 b3 b2 BITS CL02 CL01 b1 CL00 b0 clock recovery: VCLKREC = 0.25 + 116VDDD (8b3 + 4b2 + 2b1 + b0) V DESCRIPTION
Table 18 I2C-bus read parameter; ADC AGC; 4-bit value PARAMETER ADC AGC AG03 b3 b2 BITS AG02 AG01 b1 AG00 b0 AGC: VAGC = 0.25 + 116VDDD (8b3 + 4b2 + 2b1 + b0) V DESCRIPTION
Table 19 I2C-bus read parameter; 8-bit value PARAMETER SER
(1)
BITS LE7 b7 LE6 b6 LE5 b5 LE4 b4 LE3 b3 LE2 b2 LE1 b1 LE0 b0
DESCRIPTION SER = f (b7 to b0)
Note 1. The bits LE7 to LE0 give the number of symbols falling inside the lock detector active areas. The count is made during an observation period (256 to 2048 symbols). To obtain more details about the SER estimation, refer to "Application Note AN96048". Table 20 I2C-bus read parameter; 12-bit value PARAMETER IF_FREQ_SHIFT(1) Note 1. The bits FS11 to FS0 indicate the remaining frequency shift of the QAM spectrum (IF spectrum). This data is useful if the TDA8046H does not use the outer loop of carrier recovery (bit `OUTE' of the I2C-bus table set to 0). To obtain more details about the frequency shift calculation, refer to the "Application Note AN96048". 1996 Nov 19 35 BITS FS11 to FS0 DESCRIPTION frequency shift = f (FS11 to FS0)
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD Vmax Ptot Tstg Tamb 9 PARAMETER digital supply voltage maximum voltage on all pins total power dissipation storage temperature operating ambient temperature Tamb = 70 C CONDITIONS 0 - -55 0 MIN. -0.3
TDA8046
MAX. 6.0 VDDD 1.4 +150 70 V V W C C
UNIT
THERMAL CHARACTERISTICS PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 50 UNIT K/W
SYMBOL Rth j-a
10 DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS SYMBOL roll-off pass-band ripple stop-band ripple ISIpower power inter-symbol interference (15% roll-off filter) note 1 power inter-symbol interference (20% roll-off filter) note 1 Note 1. Definition of the power inter-symbol interference:
( N conv - 1 ) 2
PARAMETER
CONDITIONS - - - -
MIN.
TYP. 0.05 -43 -44
MAX. - - -
UNIT % dB dB dB
15 or 20 -
see Figs 5 and 6
2x
C conv (4k)
2
k=1 ISI power ( dB ) = 10 log -------------------------------------------------------------------2 C conv (0)
Where Nconv is the number of coefficients Cconv. Cconv(k) represent the coefficient resulting from the convolution of the transmission and reception filters (K indicates the Kth coefficient). The power ISI specified in Table 1 has been calculated on a filter resulting from the convolution of the TDA8046 filters and a truncated half-Nyquist filter with 57 T/4 taps for the 15% roll-off filter and 41 T/4 taps for the 20% roll-of filter (see "Application note AN96048" - Appendix B).
1996 Nov 19
36
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
11 LOCK DETECTOR CHARACTERISTICS SYMBOL SNRlock PARAMETER signal-to-noise ratio to lock the demodulator CONDITIONS 4-QAM 16-QAM 32-QAM 64-QAM 256-QAM 12 CARRIER RECOVERY CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. 8 15 18 21 27 MIN. - - - - - TYP. - - - - -
TDA8046
MAX.
UNIT dB dB dB dB dB
MAX.
UNIT
Carrier recovery detector CARRIER RECOVERY: BIAS CURRENT FOR DACS SET TO 37.5 A Kd detector constant SNR = 21 dB for 64-QAM constellation SNR = 27 dB for 256-QAM constellation fCAR fn(inner) fn(outer) Izero ICAR fDAC IoCARlock IoCARlock IoCARunlock frequency range loop bandwidth of inner loop loop bandwidth of outer loop zero current of DAC maximum DAC output current (programmable) DAC sampling rate rs = 5 Msym/s - - 0.017rs 10 - -100 50 - - -2.5 - -2.5 3ICAR 6.05ICAR - - - - - rs
1 2ICAR
- - - - +100 200 - - +2.5 - +2.5
A/rad A/rad MHz kHz nA A MHz A % A %
0.3fn(inner) kHz
CARRIER RECOVERY DAC OUTPUT CURRENTS DURING LOCK mean output current matching of output currents - ICAR -
CARRIER RECOVERY DAC OUTPUT CURRENTS DURING UNLOCK mean output current IoCARunlock matching of output currents
1996 Nov 19
37
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
13 CLOCK RECOVERY CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8046
MAX.
UNIT
Clock recovery detector CLOCK RECOVERY: BIAS CURRENT FOR DACS SET TO 37.5 A Kd detector constant SNR = 21 dB for 64-QAM constellation; SNR = 27 dB for 256-QAM constellation - 0.24ICLK - A/rad
fCLK fn ICLK(max) fDAC IoCLKlock IoCLKlock
frequency range natural frequency maximum DAC output current (programmable) DAC sample rate mean output current matching of output currents
100 - 50 - - -2.5
- 400 - rs ICLK -
- - 200 - - +2.5
ppm Hz A MHz A %
CLOCK RECOVERY DAC output currents
14 AGC CHARACTERISTICS SYMBOL AGC detector AGC DETECTOR: BIAS CURRENT FOR DACS SET TO 37.5 A RAGC Izero IAGC(max) fDAC IoAGC IoAGC AGC range of detector zero current maximum DAC output current (programmable) DAC sample rate 20 -100 50 - in lock unlock matching of output current - - -5 - - - rs
1 14IAGC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
- +100 200 - - - +5
dB nA A MHz A A %
AGC DAC output currents mean output current IAGC
1996 Nov 19
38
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
15 INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8046
MAX.
UNIT
Integrated loop amplifiers LOOP AMPLIFIERS GOL GB Vref Vo RL(VSSD) RL(VDDD) ZSW open loop gain gain bandwidth product reference voltage output voltage load to ground load to supply - - - 0.1VDDA 5 6.5 - 10 60 1 2.5 - - - 5 - - - - 0.9VDDA - - - - dB MHz V V k k
ANALOG SWITCHES switch impedance closed open k M
16 CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS VDDD = VDDA = 5 V; VDDD(core) = 3.3 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - - - - - TYP. MAX. UNIT
Clock outputs: CLKADC and CLKSDV VOL VOH TCLK tw tr tf RL Vi(rms) TCLK tw Rsource VIL VIH tSU tHD CL LOW level output voltage HIGH level output voltage cycle time pulse width rise time fall time load resistance 40 : 60 duty cycle CL = 30 pF CL = 30 pF 0 0.9VDDD 35 14 - - 1 0.1VDDD VDDD - - 6 6 - - - - 50 V V ns ns ns ns k
Clock input: CLK input voltage level (RMS value) cycle time pulse width source resistance 40 : 60 duty cycle sine wave 100 35 14 - - 2.0 15 0 - mV ns ns
Digital inputs: DIN8 to DIN0 LOW level input voltage High level input voltage set-up time hold time load capacitance 0.8 - - - 10 V V ns ns pF
1996 Nov 19
39
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
Digital outputs: DO1 to DO0 with respect to CLKOUT for semi-serial mode VOL VOH tod toHD CL VOL VOH tod toHD CL VOL VOH tod toHD Loop amplifier Vo Gv GB RL output voltage level DC voltage gain (open loop) gain bandwidth product load resistance 0.1VDDA - 1 5 0.9VDDA - - - dB MHz K 60 - - LOW level output voltage HIGH level output voltage output delay time output hold time load capacitance additional 0 0.9VDDD - - 2 0.1VDDD VDDD 7 10 30 V V ns ns pF
Digital outputs: DO7 to DO0 with respect to CLKSDV for 8-bit parallel mode LOW level output voltage HIGH level output voltage output delay time output hold time load capacitance additional 0 0.9VDDD - - 2 0.1VDDD VDDD 22 22 30 V V ns ns pF
Digital outputs: DO7 to DO0 with respect to CLKOUT for I/Q multiplexed mode LOW level output voltage HIGH level output voltage output delay time output hold time 0 0.9VDDD - - 0.1VDDD VDDD 22 22 V V ns ns
1996 Nov 19
40
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
BER
no convergence
MBG989
measured
10-4 implementation loss theory
SNR (dB)
Fig.31 Definition of the Implementation Loss.
handbook, full pagewidth
tr CLKADC 10% tw 90% 90%
tf VOH 10% VOL
tCLK DIN 0 to DIN 8 tSU; DAT tHD; DAT
MGG176
VIH VIL
Fig.32 CMOS input data timing diagram.
1996 Nov 19
41
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
Tsym VOH
CLKOUT VOL VOH DO1 to DO0 slot 0 toHD tod VOH CLKSDV
MGG179
slot 1
slot 2
slot 3 VOL
VOL
Fig.33 CMOS semi-serial mode timing diagram.
handbook, full pagewidth
Tsym VOH CLKSDV VOL
VOH DATA OUTPUT toHD tod VOL
MGG177
Fig.34 CMOS 8-bit symbol in parallel mode timing diagram
1996 Nov 19
42
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
TDA8046
handbook, full pagewidth
Tsym VOH
CLKOUT VOL VOH CLKSDV VOL toHD tod VOH DO7 to DO0 I Q VOL
MGG178
Fig.35 CMOS I and Q multiplexed timing diagram.
1996 Nov 19
43
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
17 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
TDA8046
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
pin 1 index
wM bp
64 1 wM D HD ZD 19
20
e
bp
vMA B vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Nov 19
44
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
18 SOLDERING 18.1 Introduction 18.3 Wave soldering
TDA8046
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 18.2 Reflow soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Repairing soldered joints
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Nov 19
45
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8046
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 19
46
Philips Semiconductors
Product specification
Multi-mode QAM demodulator
NOTES
TDA8046
1996 Nov 19
47
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/02/pp48
Date of release: 1996 Nov 19
Document order number:
9397 750 01499

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